This invention relates to communications, and more particularly, to systems for assisting users in selecting and designing components for communications systems.
Communications links in communications systems include transceiver circuits and channel media. A communications link may be considered to be made up of three link subsystems: a transmitter (TX), a channel (CH), and a receiver (RX). The transmitter is used to transmit data onto the channel from circuitry at the transmitter. The channel conveys the transmitted data to the receiver. The receiver accepts the transmitted data from the channel and provides the received data to circuitry at the receiver.
When used in a system, link subsystems may introduce signal impairments such as jitter and noise. These impairments have deterministic and random components. For example, jitter may include random jitter (RJ) and deterministic jitter (DJ) components. Random jitter may be characterized by unbounded probability distribution functions such as a Gaussian function. Deterministic jitter, which can arise from sources such as intersymbol interference (ISI), duty cycle distortion (DCD), periodic jitter (PJ), and cross talk, may be characterized by a bounded probability distribution function.
When designing a given communications link, a system designer may attempt to optimize each subsystem to meet a set of link performance criteria. For example, a system designer may select transmitter, channel, and receiver components with low noise and jitter characteristics when attempting to design a high-speed link with a stringent bit error rate (BER) limit. Many high-speed link standards specify minimum acceptable performance criteria for signals at the transmitter output and at the receiver input. The system designer may ensure compliance with a desired link standard and therefore acceptable link performance by selecting components with the ability to meet these minimum criteria.
While this type of design methodology may be satisfactory in certain situations, it can be difficult or impossible to identify workarounds when a particular link subsystem does not pass a compliance test associated with a particular high-speed link standard. In general, if a particular link subsystem is not able to meet the necessary performance benchmarks for that subsystem, there is no way to readily determine whether it might be possible to overcome this shortcoming by improving the performance of other link subsystems. As a result, if a system designer has locked down part of a design, the designer may be unable to identify a complete set of acceptable link subsystems that could be used to complete the design.
For example, a link standard might specify a particular noise and jitter level at a transmitter output and at a receiver input for a link. The receiver circuit may be fixed, due to considerations such as part availability or customer preference. If the receiver circuit is not compliant with the receiver performance criteria set forth in the link standard, conventional wisdom might dictate that the link should fail. This overlooks the possibility that improvements to the transmitter subsystem might be made that could compensate for the deficiencies of the receiver and thereby allow the link to be operated satisfactorily.
Another challenge arises when link subsystems exceed required minimum performance specifications. For example, both a transmitter and a receiver may perform better than the minimum acceptable level required by a link standard. In this situation, there is no established mechanism for providing a system designer with design assistance to take advantage of the extra performance margin available in the link.
Some link systems are designed around programmable logic device integrated circuits. In systems such as these, a logic designer would like to know how to select an optimum device family and how to best implement a desired custom logic design in that device family while satisfying link performance criteria.
It would therefore be desirable to be able to provide improved design assistance for designers of communications links and link subsystems.